The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
Support for vectorized instructions, such as single instruction, multiple data (“SIMD”) instructions, is expanding in computing architectures. However, the percentage of computer code that is vectorized (e.g., converted to SIMD) to take advantage of this expansion remains low. While tools exist to analyze source code for vectorization opportunities, source code may not always be available, and in some instances only non-human-readable, readily-executable instructions such as binary instructions (e.g., machine code) and/or bytecode are available.